A ring oscillator can be formed by connecting an odd number of inversions in a ring. This creates an unstable state to produce an oscillation. The oscillation frequency depends on the delay around the ring. The output can be taken at any point in the ring. A ring oscillator made of differential 2N stages, where N is greater than zero, of which only an odd number can invert, has quadrature outputs available. If only single-ended outputs are available, then 4N stages are required. Such ring oscillators are used to generate clocks for digital systems and signals for communication systems. The building block for the ring oscillator is a delay element also known as a delay cell.
In bipolar technology differential amplifiers have been used as the time delay element in the ring oscillator. The differential amplifiers are connected either inverting or non-inverting. The differential amplifier comprises an emitter coupled transistor pair, with the emitters connected to a current source. The bases are connected to a differential input. The collectors are connected via load resistors to a positive voltage source. The differential output is taken across the collectors via buffer transistors. The current source is varied to control the delay. As the current is increased, the speed of the stage increases, resulting in time delay decrease and a ring oscillator frequency increase. However, the output swing is defined by source current multiplied by load resistance. Because load resistance is not variable, the output level decreases with decreases in source current. This reduces the usable frequency range because the output becomes too low to drive the next stage in the ring. The low frequency usable range is also hindered because too high of a signal swing on the internal nodes comprising the collectors of the emitter-coupled pair on the load resistors can cause the transistors of the emitter-coupled pair to leave their intended linear operating region. This makes the stage both slower and its output unsymmetrical, and requires a more complex biasing scheme to control, or even a higher supply voltage.
Another prior design removes output level variance on frequency. A bias current is switched between two paths. The first path is a high speed path and the second path is a lower speed path comprised of two stages. The final output frequency is determined by a current switch which sets the portion of bias current flowing through the high speed paths single stage and the second stage of the slower path. Because the high speed stage and the second stage of the slower path share the load, the output is always determined by the total bias current multiplied by the load resistance. Because both are constant, the output is constant versus frequency. However, this circuit requires an additional bias current through the first stage of the slow path. Also, such delay cell is limited by a two-stage slow path. The minimum difference between the fast and slow path is limited by the maximum speed of the first stage of the slow path.
The present invention is directed to overcoming the problems discussed above in a novel and simple manner.